Currently the miniaturization in consumer electronic products, particularly wireless communications devices, demands highly integrated ultra-thin packages with embedded passives such as resistors, capacitors, and inductors. Hence, integration of capacitors in thin film form (embedded within the substrate) is required to achieve novel compact packaging modules with high packaging density, high performance, and reliability at low cost. Wide ranges of capacitors are needed (from a few pF to the uF range) for a variety of functions such as decoupling, switching noise suppression, impedance matching, by-pass filtering, tuning, feed back, and termination in electronic circuitry.
Substrates for Embedded Capacitor Applications:
At present three types of substrates are being utilized in the development of thin film embedded capacitors:
Type 1. Metal Foils. Fabrication of thin film embedded capacitors on printed circuit boards via dielectric coating on metal foils such as nickel or copper.
Type 2. Ceramic Substrates: Fabrication of embedded capacitors on ceramic substrates such as multilayer ceramic substrates (LTCC) or individual ceramic substrates that can be used as interposers.
Type 3. Silicon Wafers: Fabrication of thin film metal oxide capacitors on silicon wafers. The metal foils and ceramic substrates have high surface roughness and thus are not suitable for depositing/fabricating reliable thin film capacitors.
The present invention utilizes silicon wafers as substrates. The rationale for the selection of silicon wafers as substrates is as follows:
                Surface roughness/surface irregularities of substrates play major roles on the leakage current density and breakdown field strength of capacitors as well as yields of thin film capacitors. The leakage current density and breakdown field strength of the capacitors are qualitatively correlated to the amount and degree of surface irregularities on the substrates. Large local electric fields result from surface irregularities and cause the capacitors to have higher leakage current densities and fail at lower applied bias voltage. Since these electrical requirements are very important for the reliability of embedded capacitors, and since the use of submicron thickness of high dielectric constant paraelectric/ferroelectric metal oxides is required to achieve desirable capacitance density, silicon wafers are desirable substrates.        Thus, high capacitance densities can be achieved with submicron thickness of high-k metal oxides.        Direct patterning of dielectric layers to define capacitance density is highly desirable and the use of silicon wafers as substrates offers the opportunity to develop direct patterning capability.        Considering the advent of wafer level packaging (WLP), which is a true chip scale packaging (CSP), our focus is to develop thin film capacitors on silicon wafers. Moreover, it is compatible with the application of SBA materials in microelectronic technology. Some of the key knowledge practiced in low-k fabrication using SBA Materials can advantageously be used in the capacitor fabrication technology. Moreover, silicon wafer-based manufacturing is well developed and applicable to thin film metal oxide processing.        However, critical challenges associated with the silicon wafer as substrate are (a) high tensile stress due to thermal expansion mismatch between silicon and high-k films. However, since the thickness of the films on silicon is the submicron range, the tensile stress due to thermal mismatch can be tolerated with strong adhesion which is usually obtained with chemical solution derived films. (b) Limitation in thermal annealing at high temperatures due to interfacial reactions between (i) silicon and conducting metal films, and (ii) conducting metal such as Pt and the dielectric layer.Deposition Methods for Fabricating High-k Metal Oxide Thin Film Capacitors        
The following types of deposition methods are the principle approaches being investigated for the development of thin film embedded capacitors:
(a) Sputtering Technique:                Sputtering is a well-established technique in semiconductor industry and is easily adaptable to device fabrication. The technique is advantageous in making single component dense metal oxide such as tantalum oxide and hafnium oxide films using the r.f magnetron sputtering technique, however, the deposition of multi-component metal oxides such as barium titanate and barium-strontium titanate (ferroelectrics), with controlled compositions of minor additives, faces technical challenges because the fabrication of sputter targets with a precise composition having small amounts of additives is extremely difficult and very expensive.        Moreover, the deposition of sputtered films having same compositions as those of the targets is uncertain and not reproducible.        
(b) Chemical Vapor Deposition Techniques:                A variety of chemical vapor deposition techniques have been used in the deposition of dielectric films in semiconductor fabrication processes for making high-k gate oxides. Some of them are as follows:                    Metal Organic Chemical Vapor Deposition (MOCVD)            Atomic Layer Deposition (ALD)                        It should be noted that these techniques are complicated process and need very expensive equipment. They are being developed to satisfy very rigorous requirements of high-k gate oxides for semiconductor fabrication, but are slow and expensive for packaging technology, which demands low cost and less capital investment.        
(c) Chemical Solution Deposition (CSD) Method/Sol-Gel Method:                The CSD/Sol-Gel Method offers technical and cost advantages over the sputtering method but is limited by inherent technical limitations when processing on silicon wafers. Some of the disadvantages are as follows:        i. Random void/nanoporosity development during thermal annealing and thus the densification is incomplete when silicon wafers are used as substrates because of thermal budget limitations. Wide distribution of pore sizes and random distribution of pores causes a non-uniform distribution of both drying stress and annealing stress. Consequently, cracking is a serious problem.        ii. Cracking is a serious problem with CSD/Sol-Gel deposition because of non-uniform drying stress (capillary pressure during drying of solvents) develops in films having non-uniform pore structures. Consequently, a large number spin coatings i.e. multiple layers are to be deposited sequentially to achieve the desired film.        iii. Cracking is more pronounced with silicon wafers because of the thermal expansion mismatch between silicon and CSD metal-oxide films.        d) Photochemical Metal Organic Deposition (PMOD) of Thin Films (Mukherjee et al. “High Dielectric Constant Metal Oxide Films via Photochemical Metal Organic Deposition (PMOD) Process” in Physics and Technology of High-k Gate Dielectrics I, Proc. Of International Symposium on High Dielectric Constant Materials: Materials science, Processing reliability and manufacturing Issues” Edited by S. Kar et al, ECS conf Proc. Vol 2002-28)                    This method is based on the photoconversion of high-k metal organic precursor solutions that are spin coated on wafers. This method has the advantage of conversion of metal organic precursors to amorphous metal oxides at low temperatures by UV radiation to single or mixed oxide metal oxide films. This process has an added advantage of photopatterning of the dielectric films using conventional UV lithographic exposure. However, this also has the usual limitations that are typical of the conventional sol-gel/CSD method.                        